Looking Beyond CMOS Technology for Future HPC
April 5-6, 2016
The Hotel at Arundel Preserve
7795 Arundel Mills Blvd, Hanover, MD 21076
The High Performance Computing (HPC) Community in the United States is currently marshaling itself to address recently announced national grand challenges and computing initiatives. These new HPC roadmaps include the National Strategic Computing Initiative to build within the next decade exaflop (1018 operations per second) supercomputers that can analyze up to one exabyte (1018 bytes) of data. Another recent grand challenge announced by the Office of Science and Technology Policy is the Nanotechnology-Inspired Grand Challenge for Future Computing to chart a path beyond conventional transistor-based processors to implement a computer that can reason, learn, interpret, and operate with the energy efficiency of the human brain [source nano.gov]. The HPC community is also adapting itself to the new definition of High Performance Computing as announced by the President's Council of Advisors on Science and Technology (PCAST). According to the PCAST, high-performance computing "must now assume a broader meaning, encompassing not only flops, but also the ability, for example, to efficiently manipulate vast and rapidly increasing quantities of both numerical and non-numerical data [source whitehouse.gov].
The U.S. HPC community now must look beyond traditional CMOS-based computing logic and the decades-old Von Neumann architecture to meet the rapid pace of innovation needed to satisfy the national computing goals and priorities. Novel technologies will need to be developed that are based on new kinds of nanoscale devices (for example, photonic crystals, carbon nanotubes) and nanomaterials, information conduits other than the electron charge such as superposition of quantum states, superconducting computing, and new 3-D architectures integrating emerging processors and memory.
The goal of this workshop will be to explore common areas of interest among various stake holders to enable the supercomputers of the future. As such, this workshop will focus on novel approaches that overcome the limitations of CMOS technology with the potential to enable paradigm shifts in the HPC realm. The workshop will have four sessions based on the following focus areas: nanomaterials, quantum computing, superconducting computing, and emerging processor and memory architectures. Experts from federal agencies, national laboratories, industry, and academia will be invited to give talks in these areas. Common to the four focus areas will be the consideration of technological gaps and challenges to developing supporting ecosystem and infrastructure for "beyond CMOS" technologies.