Post Moore Interconnects Workshop

Agenda

2:00–2:10 PM        Opening Remarks

Dr. Neena Imam, Oak Ridge National Laboratory      

2:10–2:40 PM        Keynote

Dr. William Harrod, IARPA, United States

Bio: William Harrod is a program manager at IARPA. Previously, he served as the Research Division Director for the Advanced Scientific Computing Research Program in the Office of Science of the United States Department of Energy. Dr. Harrod was also a program manager at DARPA.           

Session 1: Interconnect Solutions for Post Moore Computing
Session Chair: Professor Sebastian Le Beux, University of Lyon, France

2:40-3:00 PM         Talk 1 - Silicon Interposer Integration Combined with Novel System Architecture for Energy-Efficient and Heterogeneous Compute Node: The ExaNoDe Solution

Dr. Denis Dutoit, ExaNoDe Project Coordinator, CEA-Tech

Abstract: Exponential growth of computing requirements for HPC causes a paradigm shift for compute node in a move from tightly focused generic compute to energy-efficient heterogeneous compute. Several combined disruptive changes in interconnect technologies (e.g. silicon interposer) and system architecture (e.g. heterogeneity, Global Address Space) are proposed for next generations of computing components. This talk will present the European ExaNoDe project with a particular focus on its solutions to combine silicon interposer integration with novel system architectures.

Bio: Dr. Denis Dutoit joined CEA-Leti in 2009, after working for STMicroelectronics and STEricsson. In CEA-Leti, he has been involved in system-on-a-chip architecture for computing and 3D integrated circuit projects. Dr. Dutoit has been the lead architect of several design projects that combine low power, 3D integration, many core architecture, and network-on-chip. He coordinates the ExaNoDe European collaborative project developing core technologies for exascale compute nodes.

3:00-3:20 PM         Talk 2 - Multi-Scale Photonic Interconnect Solutions

Professor Ian O'Connor, Ecole Centrale de Lyon, France

Abstract: This talk will focus on the current state of the art of silicon photonics technology and its potential for on-chip and off-chip optical interconnects. Particular attention will be given to multiplexing techniques available with optical signal transmission to boost bandwidth density. The talk will discuss interconnect applications at various scales: inter-rack (in high-performance computing), chip-to-chip and intra-chip for manycore architectures, and will also highlight integration difficulties such as cost, thermal sensitivity, and energy consumption.       

Bio: Professor Ian O'Connor (IEEE S'95-M'98-SM'07) is Professor for Heterogeneous and Nanoelectronics Systems Design in the Department of Electronic, Electrical, and Control Engineering at Ecole Centrale de Lyon, France. He is currently head of the Heterogeneous Systems Design group at the Lyon Institute of Nanotechnology, and Director of the SOC2 research network. Since 2008, he also holds a position of Adjunct Professor at Ecole Polytechnique de Montréal, Canada. His research interests include novel computing and interconnect architectures based on emerging technologies, associated with methods for design exploration. He has authored or co-authored over 200 book chapters, journal publications, conference papers and patents, has held various positions of responsibility in the organization of several international conferences and has been scientific coordinator for several national and European projects. He also serves as an expert with the French Observatory for Micro and Nano Technologies (OMNT), IFIP (International Federation for Information Processing), and ALLISTENE (Alliance for Digital Science and Technology).

3:20-3:40 PM         Talk 3 - A Network Accelerator Programming Interface

Professor Torsten Hoefler, ETH Zurich, Switzerland

Abstract: Optimizing communication performance is imperative for large-scale computing because communication overheads limit the strong scalability of parallel applications. Today's network cards contain rather powerful processors optimized for data movement. However, these devices are limited to fixed functions, such as remote direct memory access. We develop sPIN, a portable programming model to offload simple packet processing functions to the network card. To demonstrate the potential of the model, we design a cycle-accurate simulation environment by combining the network simulator LogGOPSim and the CPU simulator gem5. We implement offloaded message matching, datatype processing, collective communications, and demonstrate transparent full-application speedups. Furthermore, we show how sPIN can be used to accelerate redundant in-memory filesystems and several other use cases. Our work investigates a portable packet-processing network acceleration model similar to compute acceleration with CUDA or OpenCL. We show how such network acceleration enables an eco-system that can significantly speed up applications and system services.

Bio: Torsten is an Associate Professor of Computer Science at ETH Zürich, Switzerland. Before joining ETH, he led the performance modeling and simulation efforts of parallel petascale applications for the NSF-funded Blue Waters project at NCSA/UIUC. He is also a key member of the Message Passing Interface (MPI) Forum where he chairs the "Collective Operations and Topologies" working group. Torsten won best paper awards at the ACM/IEEE Supercomputing Conference SC10, SC13, SC14, EuroMPI'13, HPDC'15, HPDC'16, IPDPS'15, and other conferences. He published many peer-reviewed scientific conference and journal articles and authored chapters of the MPI-2.2 and MPI-3.0 standards. He received the Latsis prize of ETH Zurich as well as an ERC starting grant in 2015. His research interests revolve around the central topic of "Performance-centric System Design" and include scalable networks, parallel programming techniques, and performance modeling. Additional information about Torsten can be found on his homepage at htor.inf.ethz.ch.

3:40-4:00 PM         Talk 4 - Photonics Co-Packaging and In-Networking Computing

Gilad Shainer, Mellanox

Abstract: As the HPC industry progresses toward exascale, the number of bits per second increases faster than the power per bit decreases. New physical layer solutions are required to make the jump to exascale feasible and sustainable. In this talk we discuss how photonics co-packaging addresses this problem and enables other enhancements to HPC and AI, as well as other topics, such as in-network computing.

Bio: Gilad Shainer has served as Mellanox's vice president of marketing since March 2013. Previously, Mr. Shainer was Mellanox's vice president of marketing development from March 2012 to March 2013. Mr. Shainer joined Mellanox in 2001 as a design engineer and later served in senior marketing management roles between 2005 and 2012. Mr. Shainer serves as the chairman of the HPC Advisory Council organization, he serves as a board member in the OpenPOWER, CCIX, OpenCAPI and UCF organizations, a member of IBTA and contributor to the PCISIG PCI-X and PCIe specifications. Mr. Shainer holds multiple patents in the field of high-speed networking. He is also a recipient of 2015 R&D100 award for his contribution to the CORE-Direct collective offload technology. Gilad Shainer holds a M.Sc. degree and a B.Sc. degree in Electrical Engineering from the Technion Institute of Technology in Israel.

4:00-4:30 PM         Break

4:30-5:00 PM         Invited Talk - The Quantum Learning Machine

Dr. Jean-Noël Quintin, Atos

Abstract: Top500 Supercomputers are currently composed of processors, accelerators (such as GPUs) and an interconnect. These platforms are in constant evolution to provide more performance. To this aim, several kinds of accelerators/processors are emerging, such as neuromorphic and quantum processors. The latter are one of the most promising technologies as they may provide exponential speed-up for certain tasks. Prototypes for these quantum processors are available from firms such as Intel, Google and IBM. During more than 30 years, classical software and applications have been developed to expand the scope of classical processors. Even recently, applications such as machine learning have pushed back the limits of classical computing. Similarly, the near-to-medium term quantum applications have to be precisely characterized. With the Quantum Learning Machine (QLM), Atos provides tools to analyze and to disclose the potential advantage of realistic quantum processors. The aim is to create a full software stack for quantum platforms with hardware analysis (noise, architecture), general and hardware-specific circuit optimizations, to investigate the different quantum hardwares and the distributed platform architectures, as well as to develop applications and unified interfaces.

Bio: Jean-Noël Quintin is a senior researcher working in the Atos quantum lab. Dr. Quintin received his M.S. in 2008 and his Ph.D. in 2011 from the Grenoble University in France. Before working for Bull, he has done a Post-Doc at University College of Dublin in 2012. His research focuses on improving communication patterns in dynamics scheduling methods, within large-scale applications and interconnect routing algorithms. His transition to the Atos quantum lab have been motivated by the opportunity to handle communication patterns for hybrid quantum/classical applications.

Session 2: Balance of the System Design
Session Chair: Dr. Barney Maccabe, Oak Ridge National Laboratory, United States

5:00-5:20 PM         Talk 1 - Random Access Memories for Superconducting Computing

Dr. Yehuda Braiman, Oak Ridge National Laboratory, United States

Abstract: In our presentation we will discuss random access memory designs based on superconducting Josephson junction technology. Superconducting digital logic circuits show promise to significantly advance performance in various electronics and computing applications. However, designing random access memories still poses substantial challenges in reducing power dissipation, increasing access speed, and reducing the size of the chip. In our talk we will review the state-of-the art of cryogenic memory designs and briefly discuss our group's proposed cryogenic memory cell design that has the potential to address some of the challenges listed above.

Bio: Yehuda Braiman is a Distinguished R&D Scientist in the Computational Sciences and Engineering Division at Oak Ridge National Laboratory and a Joint Faculty Professor in the Department of Mechanical, Aerospace, and Biomedical Engineering at the University of Tennessee, Knoxville. His primary research interests are in the fields of nonlinear dynamics and synchronization of extended dynamical systems, phase locking of semiconductor diode laser arrays, and cryogenic memory design employing superconducting circuits.

5:20-5:40 PM         Talk 2 - Heterogeneous Post-CMOS Technologies Meet Software

Professor Jeronimo Castrillon, TU Dresden, Germany

Abstract: Plenty of novel emerging technologies are being proposed and evaluated today, mostly at the device and circuit levels, for logic, memory, and interconnect. It is unclear what the impact of different new technologies at the system level will be. What is clear, however, is that new technologies will make their way into systems and will increase the already high complexity of heterogeneous parallel computing platforms, making it ever so difficult to program them. This talk describes the efforts done in the context of the large-scale German project "Center for Advancing Electronics Dresden" (cfaed) to bridge the interdisciplinary gap between computer science and technologists and to start designing hardware/software abstractions. We are convinced that such early software considerations are key to prevent advanced technologies to serve ever smaller application niches.

Bio: Jeronimo Castrillon is a professor in the Department of Computer Science at the TU Dresden, where he is also affiliated with the Center for Advancing Electronics Dresden (CfAED). He received the Electronics Engineering degree from the Pontificia Bolivariana University in Colombia in 2004, the Master's degree from the ALaRI Institute in Switzerland in 2006, and the Ph.D. degree with honors from the RWTH Aachen University in Germany in 2013. His research interests are in methodologies, languages, tools, and algorithms for programming complex computing systems. He has more than 70 international publications and has been a member of technical program and organization committees in international conferences and workshops (e.g., CGO, DAC, DATE, ESWeek, LCTES, Computing Frontiers, FPL and ICCS). He is also a regular reviewer for ACM and IEEE journals (e.g., IEEE TCAD, IEEE TPDS, ACM TODAES and ACM TECS).

5:40-5:55PM          Talk 3 - Carbon Nanotube Processor Meets HPC

Dr. Neena Imam, Oak Ridge National Laboratory, United States

Abstract: Future computing demands far exceed the capabilities of today's electronics, and cannot be met by isolated improvements in transistor technologies, memories, or integrated circuit (IC) architectures alone. The N3XT (Nano-Engineered Computing Systems Technology) approach overcomes these challenges through recent advances across the computing stack: (a) transistors using nanomaterials such as one-dimensional carbon nanotubes (and two-dimensional semiconductors) for high performance and energy efficiency, (b) high-density non-volatile resistive and magnetic memories, (c) ultra-dense (e.g., monolithic) three-dimensional integration of logic and memory for fine-grained connectivity, (d) new architectures for computation immersed in memory, and (e) new materials technologies and their integration for efficient heat removal. N3XT hardware prototypes represent leading examples of transforming scientifically-interesting nanomaterials and nanodevices into actual nanosystems. Thus talk will discuss the collaboration between Oak Ridge National Laboratory and Stanford University in evaluating the potential of the CNT processor for HPC applications.

Bio: Dr. Neena Imam is a distinguished research scientist in the Computing and Computational Sciences Directorate (CCSD) at Oak Ridge National Laboratory (ORNL), performing research in extreme-scale computing. Neena Imam has also been serving as the Director of Research Collaboration for ORNL's Computational Science's Directorate (CCSD) for the last five years. Neena Imam holds a Doctoral degree in Electrical Engineering from Georgia Institute of Technology, with Master's and Bachelor's degrees in the same field from Case Western Reserve University and California Institute of Technology, respectively. Neena also served as the Science and Technology Fellow for Senator Lamar Alexander in Washington D.C. (2010-2012).

5:55 PM                   Closing Remarks and Adjourn