Beyond CMOS Computing: The Interconnect Challenge
The 2017 workshop will have four sessions and will focus on the following topics: metrics/benchmarks, balance of the system design, interconnects, and CMOS/beyond CMOS integration.
Wednesday, November 29, 2017
7:30-8:30 AM Registration and Working Breakfast (breakfast provided)
Agenda: Discussion of Session Topics
8:30-8:45 AM Welcome, Introductions, and Report on 2016 Beyond CMOS Workshop
Dr. Neena Imam, Oak Ridge National Laboratory
Beyond CMOS Computing: Eliminating the Bottlenecks
Irene Qualters, National Science Foundation
Bio: Irene Qualters is the Director of the Office of Advanced Cyberinfrastructure (OAC) at the National Science foundation (NSF). In this role, Irene leads OAC in its mission to support and coordinate the prototyping, development, acquisition, and provisioning of state-of-the-art cyberinfrastructure resources, tools, and services essential to the advancement and transformation of science and engineering. Prior to joining NSF in 2009, Irene had a distinguished 30-year career in industry, with a number of executive leadership positions in the technology sector. During her twenty years at Cray Research, she led major research and development efforts for Cray's parallel products. Subsequently as Vice President, she led Information Systems for Merck Research Labs and 12,000 researchers, focusing on international cyberinfrastructure to advance all phases of pharmaceutical R&D. Irene is an expert in parallel computer system architectures and in a wide variety of software development arenas, from scientific applications to file systems and operating systems.
Morning Break (coffee provided)
METRICS AND BENCHMARKS FOR Beyond CMOS
FOR HPC APPLICATIONS
10:00 AM-12:00 NOON
MODERATOR: Dr. NEENA IMAM, OAK RIDGE NATIONAL LABORATORY
This session will explore the adequacy of current HPC benchmarks for beyond CMOS computing. Invited speakers will present talks on benchmark requirements going forward and will present ideas on how to ensure a suite of measurements to exercise novel hardware.
Beyond CMOS RESEARCH AND BENCHMARKING: AN SRC PERSPECTIVE
Dr. An Chen, Scientific Research Corporation
Abstract: For 35 years, Semiconductor Research Corporation (SRC) has provided a successful platform to support public-private collaboration and funded university research to advance semiconductor technologies with worldwide impact. With CMOS scaling approaching the fundamental limits, the semiconductor industry has increasingly focused on beyond CMOS research to pursue sustainable improvement in performance, efficiency, and functionality. The Nanoelectronics Research Initiative (NRI) was launched in 2006 by SRC in collaboration with NSF and NIST to research the "next switch" that can outperform CMOS transistors with lower power consumption in critical applications. For over 10 years, NRI has explored numerous novel devices based on alternative state variables, unconventional switching mechanisms, and emerging materials. NRI researchers have developed comprehensive benchmarking methodologies to assess these novel devices against the ultimately scaled CMOS transistors. While NRI research has significantly advanced beyond CMOS devices and materials, no new switch has been shown to be able to replace CMOS transistors for Boolean logic and von Neumann architectures. The energy-delay tradeoff in CMOS also extends into the beyond CMOS domain. On the other hand, many beyond CMOS devices demonstrate unique characteristics suitable for novel architectures or computing paradigms, e.g., device-level reconfigurability, built-in memory in logic switch, tunable analog behaviors, and high computational density. In order to effectively utilize these unique device characteristics in novel architectures, it is essential to co-optimize beyond CMOS devices and architectures, which may enable novel functionality and achieve improved energy efficiency at system level. With the NRI program ending this year, a follow-on program, nanoelectronic COmputing REsearch (nCORE), has been launched to pursue basic research in materials, devices, and interconnects, to enable novel computing paradigms beyond conventional CMOS technologies and von Neumann architectures.
Bio: Dr. An Chen is on assignment from the IBM Corporation to serve as the Executive Director of the Nanoelectronics Research Initiative (NRI). The NRI supports university-based research on future nanoscale logic devices to replace the CMOS transistor in the 2020 timeframe. An Chen received his Ph.D. degree in Electrical Engineering from Yale University in 2004. An started working on emerging memory technologies at Spansion LLC. In 2007, he joined AMD as a full-time assignee to the Nanoelectronics Research Initiative (NRI) program with SRC. He is also a memory Tech Lead responsible for research collaborations with industry consortia and partners on emerging memories. Since 2011, An has been the chair of the Emerging Research Device (ERD) group of the International Technology Roadmap for Semiconductors (ITRS). An has published many peer-reviewed research articles and holds 16 U.S. patents (4 pending). He is the lead editor of "Emerging Nanoelectronic Devices" (Wiley, 2015) and has contributed chapters to four books. He is on the Advisory Boards of U. Nebraska Lincoln MRSEC center and U. Florida Nanoscale Security MURI program, and has also served in the Technical Advisory Board of several SRC programs and thrusts. An is a Senior Member of IEEE.
Benchmarking for Beyond CMOS Devices in Boolean and Neuromorphic Circuits
Professor Azad Naeemi, Georgia Institute of Technology
Abstract: This talk will present the results of a uniform benchmarking methodology that captures and evaluates the latest research for various beyond CMOS device proposals. It will be shown that many of the emerging technologies face significant challenges to compete with CMOS when performing Boolean logic functions. To better utilize emerging charge- and spin-based technologies, alternative non-Boolean architectures are critically needed. Three types of cellular neural network (CeNN) implementations are investigated and benchmarked for a given input noise and recall accuracy target values. Results demonstrate that spintronic devices are promising candidates to implement CeNNs.
Bio: Azad Naeemi received a Ph.D. degree in electrical and computer engineering from the Georgia Institute of Technology (Georgia Tech), Atlanta, in 2003. He worked as a Research Engineer with the Microelectronics Research Center, Georgia Tech, from 2003 to 2008 and then joined the School of Electrical and Computer Engineering faculty at Georgia Tech, where he is currently a Professor. His research crosses the boundaries of materials, devices, circuits and systems, investigating integrated circuits based on conventional and emerging nanoelectronics and spintronic devices and interconnects. Dr. Naeemi serves as the leader of beyond CMOS benchmarking research at the SRC Nanoelectronics Research Initiative (NRI) and the Semiconductor Technology Advanced Research Network (STARnet).
Ultra-low power artificial synapses using reconfigurable magnetic Josephson junctions
Dr. Michael Schneider, National Institute of Standards and Technology
Abstract: Neuromorphic computing promises to dramatically improve the efficiency of certain computational tasks, such as perception and decision making. While software and specialized hardware implementations of neural networks have made tremendous accomplishments, both implementations are still orders of magnitude less energy efficient than the human brain. We demonstrate a new form of artificial synapse based on dynamically reconfigurable magnetic Josephson junctions. We demonstrate synaptic weight training with electrical pulses as small as 3 aJ, which compares favorably to the roughly 10 fJ per synaptic event of the human brain. The critical metrics required to evaluate this new technology will be discussed.
Bio: Michael Schneider is a Physicist at NIST in Boulder, Colorado.He received his B.S. in Physics from the University of Michigan in 1998, and his Ph.D. in Physics from the University of Wisconsin in 2003.Prior to joining NIST, he was a Sr. Member of the Technical Staff at Everspin Technologies where he worked on development of spin torque MRAM.
SYSTEM LEVEL SIMULATION/BENCHMARKING OF NEAR-TERM QUANTUM COMPUTERS
Dr. Eugene F. Dumitrescu, Oak Ridge National Laboratory
Abstract: Quantum computing promises to tackle some classically intractable computational tasks. As experimental qubit hardware continues to scale, but with fault tolerant quantum computation still out of reach, small scale noisy quantum computations are now being integrated into classical-quantum algorithms whose computational complexity remains open question. In this talk we discuss the development and validation of hybrid and small-scale quantum algorithms. Specifically, we discuss the role of our tensor network quantum virtual machine (TNQVM) targeting the Titan supercomputer at ORNL. We also discuss the unique opportunity for large scale HPC systems to perform the ultimate classical verification of near-term quantum computations and their role in future hybrid classical-quantum algorithms.
Bio: Eugene Dumitrescu is a postdoctoral researcher at ORNL in Oak Ridge, TN. He received his B.S. in Physics from the University of North Carolina in 2009, and his Ph.D. in Physics from the Clemson University in 2014. Prior to joining ORNL, he was an Intelligence Community Postdoctoral Research Fellow where he worked on quantum coding based sensing protocols.
Working Lunch (lunch provided)
Agenda: Discussion and Feedback on Morning Session
Exascale Architectures and Applications, a Forecast
George Cotter, (Retired) National Security Agency
Abstract: This talk will focus on trends in extreme scale technologies, demanding federal mission applications and their imperatives, and architectures that would be essential. It will attempt to link advances in these fields into a coherent vision for the NSCI program, and a "beyond-exascale" follow-on. It will be essential to outline the fundamental technical (and admittedly speculative) foundations for such a forecast – given the hugely significant transitions underway in our community. The talk will end with a discussion of market forces that will be encountered and must be addressed.
Bio: George R. Cotter retired from the National Security Agency (NSA) in 2009, after 62 years of cryptologic service. During his long service at NSA, George Cotter had multiple senior assignments, including NSA Chief Scientist and Director of Telecommunications and Computer Services. He was also the Founding Director of the DOD Computer Security Center. George Cotter has received many professional awards and holds memberships at multiple prestigious professional organizations. Most notably, George Cotter was inducted in the National Academy of Engineering in 2007. He served as a member of the NSA Advisory Board from 2010-2017 and the Defense Intelligence Agency (DIA) Advisory Board (10 years). George Cotter also received the National Intelligence Distinguished Service Medal, the Presidential Rank Award, the Armed Forces Communications and Electronics Association (AFCEA) Intelligence Medal, and the AFCEA Lifetime Achievement Award.
SESSION 2: BALANCE OF THE SYSTEM DESIGN
MODERATOR: DR. CELIA MERZBACHER, OAK RIDGE NATIONAL LABORATORY
This session will aim to address the path forward for moving beyond component level designs to sustained operation of an entire computing platform for the following beyond CMOS computing paradigms: quantum computing, superconducting computing, and neuromorphic computing. Other beyond CMOS computing paradigms may also be included in the discussions. The speakers will discuss the system bottlenecks and the necessary simulation/fabrications tools.
Scalable solutions for communications-intensive computations using chip-level automata processors
Dr. Lance Joneckis, Institute of Defense Analysis
Abstract: A critical element in beyond CMOS, by which we mean the end of Moore's law, is how to use CMOS more efficiently. This will largely mean innovation at the architecture and programming layers of the system. The von Neumann architecture is particularly inefficient for problems that are control dominated or consist of large inexact pattern matching or pattern discovery. These problems are typically characterized by poor spatial and temporal locality, and massive combinatorial searches. Three large and important classes of such problems are many Bioinformatics related computations, graph computations and constraint satisfaction computations. The Natural Neural Processor (NNP), being developed and brought to market by the startup company, Natural Intelligence Semiconductor, Inc. (NIS), has exceptional potential for significantly increasing the computational efficiency for these classes of computations. The NNP is a novel non-von Neumann, multiple instruction, single data (MISD) device that significantly extends the proof of concept device called the Automata Processor that Micron Technology, Inc. announced at SC2013.
This talk will discuss the architecture of the NNP and it's potential for applications of Bioinformatics, Boolean Satisfiability and graph computations. While NIS is completing the development to bring the NNP to market, a significant knowledge base and tool set exists which enables the research and development work needed to be done at the application level for the NNP to reach its potential.
Bio: Dr. Lance G. Joneckis is on the research staff in Science and Technology Division of The Institute for Defense Analyses. He focuses on cyber, communications, and high performance computing. Dr. Joneckis has also worked for startups, AT&T, and the Intelligence Community. Dr. Joneckis received a Ph.D. in Physics from The University of Maryland in 1990.
Dr. Trevor Lanting, D-Wave Systems, Inc.
Abstract: Processors that harness quantum mechanics for computational advantage hold immense promise, but present challenges in scaling to a practical size. Practical and programmable quantum hardware must be developed with a clear focus on the design of the entire system from the qubit design up to the control circuitry, the room temperature electronics, and the cryogenic enclosures. We have built a series of scalable systems that implement a single algorithm, quantum annealing (QA). QA is run on a network of superconducting flux qubits with in situ programmable pair-wise magnetic interactions. I will introduce the QA algorithm and provide an overview of the processor architecture, device design, and programmability from a systems perspective.
Bio: Dr. Trevor Lanting is a Senior Scientist at D-Wave Systems. He joined D-Wave in 2008 and has been involved with the development of the quantum annealing processor technology. He studied at UC Berkeley and obtained a Ph.D. in experimental physics in 2006. After graduate school, he received an NSERC postdoctoral fellowship and worked with the Experimental Cosmology Lab at McGill University focused on instrumentation and data analysis from 2006 to 2008.
Afternoon Break (refreshments provided)
Progress in Approximate Universal Quantum Computation
Dr. Mark Ritter, IBM
Abstract: Much past algorithm research has focused on full fault-tolerant quantum computation (FTQC), but technology has quite some hurdles to overcome to achieve FTQC. We have decided to focus our efforts toward heuristic approximate algorithms on a universal circuit-model quantum computer where little or no error correction is used, yet the problems are sufficiently hard that approximate answers may be adequate. I will first describe the team's progress toward implementing an approximate quantum computer with full system hardware and software stack, then explain how we have implemented a heterogeneous heuristic quantum eigenvalue solver. I will describe our results applying the eigensolver to quantum chemistry, Heisenberg magnets, and optimization problems to demonstrate the flexibility of this approximate approach. I will close with a discussion of error mitigation techniques which are needed to allow greater accuracy and/or larger problems, yet do not require the overhead of FTQC.
Bio: Dr. Ritter is a Distinguished Research Staff Member and senior manager of the Quantum Science group in the Physical Sciences Department at the IBM T.J. Watson Research Center. His group focuses on the experimental and theoretical science of quantum information, especially as applied to quantum computing. The IBM Quantum Experience was launched by his group in May of 2016, allowing users to access and program a five qubit quantum processor through a GUI-enabled cloud interface. Dr. Ritter received M.S., M.Phil. and Ph.D. degrees in Applied Physics from Yale University in 1987. Dr. Ritter was the recipient of the 1982 American Physical Society Apker Award for his work on the optical and magnetic properties of solids.
Superconducting Computing: Challenges and Opportunities in Systems Architecture
Dr. Robert Voigt, Northrop Grumman Corporation
Abstract: Superconducting computing is a strong contender for high performance computing beyond CMOS. But this approach presents a whole new set of opportunities and challenges for system designers in bringing this technology to the mainstream. The operating temperature of computing hardware at 4 Kelvin is one of the unique challenges to getting data in and out of the system, whereas chip to chip data movement at 4 Kelvin is improved over CMOS. Memory support at various temperatures and locations will require new approaches to system design. This talk will touch on possible approaches for architecting I/O and memory; the bottlenecks, the balance and the impact on system design.
Bio: Dr. Robert Voigt is an NG Fellow and the Product Area Architect for Transformational Computing for Northrop Grumman Mission Systems. Dr. Voigt's principal work has been in the area of advanced processing architectures for signal and data processing. In his role as a PAA for Transformational Computing, he is involved with many of the latest "beyond CMOS" technologies that include everything from machine learning to low power computing. His latest role is the Chief Architect for the Cold Logic Program working with the Reciprocal Quantum Logic (RQL) superconducting logic family. Dr. Voigt was a career Naval Officer for 30 years, retiring at the rank of Captain. As a former Engineering Duty Officer with the U.S. Navy, Dr. Voigt has acted as technical lead, systems engineer and program manager on various DoD programs. Prior to coming to Northrop Grumman, Dr. Voigt was a professor of Electrical and Computer Engineering at the U.S. Naval Academy where he also served as Chair.
Professor Mostafizur Rahman, University of Missouri Kansas City
Abstract: As CMOS scaling reaches the end, 3-D integration provides possible pathways. In this talk, we will introduce a new 3-D IC fabric that can potentially overcome scaling barriers with order of magnitude benefits. In our approach, stacked nanowires are building blocks; transistors and especially architected connectivity and heat extraction features are formed onto these nanowires for fabric functionalization. Logic and memory implementations are through CMOS logic and fabric specific mapping scheme. There are no needs for wafer/die/layer bonding and inter-substrate connectivity through peripheral wires or large TSVs. Thermal features are designed to enable heat extraction and are part of circuit design. Our circuit analyses revealed tremendous benefits; over 14.6x and 5.5x density benefits vs. 2-D CMOS and monolithic 3-D respectively at 16nm. Our cost projections showed the possibility of over 2x cost reduction compared to 2-D CMOS.
Bio: Mostafizur Rahman joined the Computer Science and Electrical Engineering (CSEE) department in University of Missouri Kansas City after receiving his Ph.D. from the University of Massachusetts Amherst in Electrical and Computer Engineering. He leads the Nanoscale Integrated Circuits (Nano-IC) lab and is a co-lead for the Center for Interdisciplinary Nanoscale Research (CINTR) at CSEE. His group's research focus is on transformative approaches for nanoelectronics to surpass the current limitations of today's integrated circuits. His current research projects include: beyond CMOS computing with 3-D integration, multi-valued logic and memory design with magneto-electric devices, Crosstalk computing, and proof-of-concept manufacturing. He has authored and co-authored over 40 peer-reviewed journal and conference publications. He is a guest editor for the IEEE Transactions on Nanotechnology's special issue on Revolutionary 3-D Integration and Design for Next Generation Computing, and also publication chair for IEEE/ACM Symposium on Nanoscale Architectures. He received several awards including best paper awards in IEEE NANOARCH 2014, 2013, and second prize in UMASS entrepreneurship contest.
EFFICIENT SYSTEM DESIGN FOR DEPLOYMENT ON IBM'S NEUROMORPHIC TRUENORTH PROCESSOR
Dr. Kathleen Hamilton, Oak Ridge National Laboratory
Abstract: Neuromorphic processors can execute deep learning tasks with high accuracy and low power consumption. However, the need for off-chip training creates a significant bottleneck and impedes incorporating these processors into heterogeneous computing workflows. We present results from a classification task on undirected graphs that can be implemented as a sparse spiking network and deployed on current generation neuromorphic hardware and constructed with weight-setting heuristics rather than iterative training.
Bio: Kathleen Hamilton obtained her Ph.D. in Physics from the University of California at Riverside studying correlated electron systems. Since joining Oak Ridge National Laboratory as a Postdoctoral Research Associate her research has focused on graphical models and their use in algorithmic design for next-generation processors. She has developed methods for efficient embedding of spiking neural networks into neuromorphic hardware for optimization tasks.
Thursday, November 30, 2017
Registration and Working Breakfast (breakfast provided)
Agenda: Discussion of Day 1 Sessions
Welcome and First Day Recap
Dr. Neena Imam, Oak Ridge National Laboratory
Revisiting Amdahl's Wafer Scale Integration with advanced packaging
Professor Subu Iyer, University of California, Los Angeles
Abstract: In the 70's, Gene Amdahl's Trilogy Systems proposed and then abandoned the concept of wafer scale integration to build a high performance mainframe on a single silicon wafer. Recent developments in advanced packaging such as the Silicon Interconnect Fabric being worked on at UCLA allow us to revisit this concept with a very high probability of success. This talk will examine the technology, challenges, and architectural benefits of the Silicon Interconnect Fabric for the heterogeneous integration of massively scaled-out high performance systems.
Bio: Subramanian (Subu) Iyer joined UCLA in 2015 and is Distinguished Chancellor's Professor and holds the Charles P. Reames Endowed Chair in Electrical Engineering with a joint appointment in the Material Science and Engineering Department. Prior to that, he was an IBM Fellow and managed Silicon and Packaging development at IBM. His technical accomplishments include Salicide, the world's first SiGe HBT, embedded DRAM, electrical fuses and 3-Dimensional Integration at IBM. He also co-founded SiBond LLC to develop and manufacture bonded SOI wafers. At UCLA, he is Director of CHIPS (chips.ucla.edu) where he develops advanced packaging and device concepts for memory, neuromorphic, RF and medical engineering applications. He is Fellow of IEEE & APS and was awarded the IEEE Daniel Noble Award for emerging technology. Subu is the treasurer of IEEE Electron Device Society and a member of the Board of Governors of the IEEE Electronics Packaging Society.
SESSION 3: INTERCONNECTS FOR Beyond CMOS COMPUTING
10:00 AM-12:30 PM
MODERATOR: STEVE PRITCHARD, DEPARTMENT OF DEFENSE
The third session of the workshop will discuss the most appropriate types of interconnects for beyond CMOS computing. Invited speakers will present talks on Graphene interconnects, optical interconnects, and silicon photonics. We will also discuss the state-of-the-art in large scale manufacturing/foundry capabilities and technology roadmap for the next 5 years.
IARPA Programs for Superconducting Computing
Marc Manheimer, Intelligence Advanced Research Projects Activity
Abstract: In pursuit of potential post-Moore's Law computing technology, Intelligence Advanced Research Projects Activity (IARPA) has been supporting the development of technology for a computer based on superconducting single flux quantum logic in its C3 program. One of the main advantages of this approach is that the data bits travel as pulses over intrinsically low-loss superconducting interconnect. IARPA has also just approved the SuperCables program to develop energy-efficient interconnect between 4 kelvins and room temperature. This talk will give a brief introduction to these programs and their promise.
Bio: Marc Manheimer, a low-temperature condensed matter physicist, has held several positions at the National Security Agency. He is currently at IARPA, managing programs to advance technology for post-Moore's Law computing.
Energy efficient, high bandwidth digital data links between 4 and 300K
Dr. Deborah Van Vechten, Office of Naval Research
Abstract: The inherent superior energy efficiency of digital circuits composed of superconducting switches is well proven compared to Si processors at room temperature (300K). However, the ability to move, without negatively impacting the system energy budget, the computational results from the 4K environment back to the room where other processors, main memory, and the users reside is not yet of low technical risk. What is needed is a break-thru in the egress mechanism that utilizes the inherent physics of materials at low temperatures to deliver improvement in the energy efficiency of moving information up the thermal gradient that more than makes up for the thermodynamically inherent inefficiency of the coolers that must remove the dissipated energy from the cryogenic environments. This problem and the possibility that electro-optics/photonics can deliver the needed functionality will be discussed.
Bio: Dr. Deborah Van Vechten has been the Office of Naval Research's program officer for SuperConducting Electronics (SCE) since 1994 in the department which deals with RF communications and other EM sensing applications. In that role, she has funded the development of both the circuit components that are at the heart of every receiver and also the packaging that allows such functionality to be taken to the fielded signal source, not just used in the laboratory. The digital data links from 4K to 300K FPGA have been a critical part of her program in recent years.
Morning Break (coffee provided)
Next generation HPC Fabric and Interconnects
Benny Koren, Mellanox
Abstract: In this talk we will explore the challenges for HPC and data center interconnect for the coming years and the role of silicon photonics and close integration of optical connectivity and switch solutions.
Bio: Benny Koren, Mellanox VP for architecture, re-joined Mellanoxin 2010 and is responsible for Mellanox's switch silicon and physical layer products. Previously, Mr. Koren was vice president of architecture at Kaminario from 2008 to 2010. From 2000 to 2008, Mr. Koren was a lead architect at Mellanox Technologies. Mr. Koren graduated Cum Laude with a B.Sc. in Electrical Engineering from theTechnion, Israel Institute of Technology.
Graphene Interconnects for 7- and 5-nm Technology Nodes
Ning Wang, Stanford University
Abstract: Interconnect resistance increasingly dominates system performance, with metal line resistance contributing as much as ~30% to circuit delay at 7-nm. In this presentation, we present a broad assessment of low-resistivity graphene interconnects for 7- and 5-nm node technologies. We replace copper interconnects with graphene in a standard silicon electronic design automation (EDA) workflow to assess system level performance. Despite ~60% reduction in delay with graphene interconnects, system level performance improvement is restricted to ~8-12%, suggesting a need for further design-technology co-optimization (DTCO) to extract maximum performance.
Bio: Ning received his B.S. in ECE from University of Texas at Austin (2011) and his M.S. from UIUC (2013). He is now pursuing his Ph.D. in EE at Stanford where his research focuses on large-scale graphene growth and electronics with emphasis on CMOS compatible applications. Current research topics include graphene interconnects and graphene mixed-signal circuits for accelerating dot-product computation.
Working Lunch (lunch provided)
Agenda: Discussion and Feedback on Morning Session
SESSION 4: INTEGRATING CMOS WITH EMERGING Beyond CMOS TECHNOLOGIES
MODERATOR: JOHN BOLGER, DEPARTMENT OF DEFENSE
Should beyond CMOS technologies be considered as co-processors/accelerators for CMOS-logic HPC? What kind of compilers, APIs, infrastructure requirements should we look at for this type of hybrid computing platforms? We will address these questions during the last session of the workshop.
implementation of hybrid quantum-classical algorithms
Abstract: In this talk, we will discuss the process of implementing algorithmic primitives of quantum-classical algorithms on near-term quantum computing hardware. We will also present experimental results of overhead associated with the graph embedding steps in quantum annealing processors.
Bios: Dr. Neena Imam is a distinguished research scientist in the Computing and Computational Sciences Directorate (CCSD) at Oak Ridge National Laboratory (ORNL), performing research in extreme-scale computing. Neena Imam has also been serving as the Director of Research Collaboration for ORNL's Computational Science's Directorate (CCSD) for the last five years. Neena Imam holds a Doctoral degree in Electrical Engineering from Georgia Institute of Technology, with Master's and Bachelor's degrees in the same field from Case Western Reserve University and California Institute of Technology, respectively. Neena also served as the Science and Technology Fellow for Senator Lamar Alexander in Washington D.C. (2010-2012).
Dr. Raphael Pooser is an expert in continuous variable quantum optics. His research interests include quantum computing and quantum information science. He currently leads the "Methods and Interfaces for Quantum Acceleration of Scientific Applications" program, part of the Quantum Computer Testbed Pathfinder program. Dr. Pooser received a B.S. in physics from New York University in 2001, and a Ph.D. in Engineering Physics from the University of Virginia in 2007. He served as a postdoctoral fellow in the Laser Cooling and Trapping group at NIST before coming to ORNL as a Wigner Fellow in 2009.
Relative Efficiency of Memristive and Digital Neuromorphic Crossbars
Dr. Christopher Krieger, Department of Defense
Abstract: Both analog and digital NMPs have been proposed in literature, with many papers indicating that memristor based analog designs provide significant efficiency gains over digital approaches. In this talk, we use extensive SPICE simulations to compare the energy efficiency and throughput per area of basic analog and digital neuromorphic processors after architectural differences have been factored out. We find that memristor-based analog designs offer about four times better throughput per watt for computation than digital systems and that they provide nearly ten times the throughput per area.
Bio: Dr. Krieger serves as a lead researcher in the Neuromorphic Computation Research Program at the Laboratory for Physical Sciences, a federal research lab located at the University of Maryland. In this role, he researches special purpose hardware for machine learning and understanding. His eclectic prior research includes work on memory locality optimizations for irregular applications, design automation tools for asynchronous circuits, and instruments for measuring deformation of nuclear fuel rods. Dr. Krieger also has more than 15 years of industry experience designing and simulating microprocessors for Hewlett-Packard and Intel.
Dr. Gary Delp, Mayo Clinic
Abstract: Composing increasingly complex electronic systems can be greatly assisted through the use of hierarchy and defined interfaces. The wonderful thing about standard interfaces is that there are so many to choose between. This talk will illustrate a methodology supporting the composition of heterogeneous systems. Verification and validation are greatly assisted through the use of descriptions of the functions and interconnection that works at many levels of the hierarchy of an HPC system. The IEEE IPXACT Standard 1684-2014 provides the XML structure and IP semantics to describe electronic components and systems. The meta-data is standardized and includes components, systems, bus interfaces and connections, abstractions of those buses, and details of the components including address maps, register and field descriptions, and file set descriptions for use in automating design, verification, documentation, and use flows for electronic systems. A set of XML schemas and a set of semantic consistency rules (SCRs) are included. A generator interface that is portable across tool environments is provided. The specified combination of methodology-independent meta-data and the tool-independent mechanism for accessing that data provides for portability of design data, design methodologies, and environment implementations.
Bio: Gary Delp is currently an engineer at the Mayo Clinic special purpose processor development group (SPPDG). Gary acts as one of several points of contact for Mayo- and US Government-sponsored projects. SPPDG is a trusted, unbiased, third-party entity, advising government and government sponsored research and development teams. Previously serving at LSI, Gary designed cell, systems, and flexible plug and play SOCs. He was technical director for the VSIA, The SPIRIT Consortium, and Accellera. With those groups and the IEEE he contributed to 15+ completed IEEE approved standards, chairing many of the working groups. IP-XACT was a collaborative standard from the spirit consortium that has made it through the IEEE process with subsequent upgrades. He was instrumental in bringing together the two competing low power consortia, leading first to independently published standards, the interoperable, and finally, combined in IEEE 1801-2012. Gary served as a research staff member and distinguished engineer at Watson, Rochester, MN. Gary is a senior member of the IEEE, and an inventor on more than 60 issued U.S. patents.
Afternoon Break (refreshments provided)
extending cmos utiliity vs. disruptive technology
Dr. Barney Maccabe, Oak Ridge National Laboratory
Bios: Dr. Scott Holmes is a technical consultant with Booz Allen Hamilton. His interests include superconducting electronics, future computing, and learning systems. He holds a joint Ph.D. in Materials Science and Nuclear Engineering & Engineering Physics from the University of Wisconsin, Madison. He is a Member of the IEEE Council on Superconductivity and for the International Roadmap for Devices and Systems (IRDS) leads the Cryogenic Electronics team. Currently he supports the IARPA Cryogenic Computing Complexity (C3) program to develop energy-efficient superconducting computing technologies.
Dr. Kosaraju is currently the Division Director of the Division of Computing and Communication Foundations (CCF) in the Computer and Information Science and Engineering (CISE) Directorate at the National Science Foundation. He is at NSF on assignment from the Johns Hopkins University where he holds the Edward J. Schaefer Chair in Engineering in the Department of Computer Science. He has broad research interests in Algorithms. He served on the editorial boards of many journals; he was the managing editor of the SIAM J. on Computing during 1980-1988. He has also served on the advisory and external committees of many computer science departments. He was recognized for teaching excellence several times. He is a fellow of ACM and IEEE.
Sébastien Le Beux is an Associate Professor for Lyon Institute of Nanotechnology at the University of Lyon. He received his Ph.D. in Computer Science from the University of Sciences and Technology of Lille in 2007. In 2017, he became an Adjunct Professor at Ecole Polytechnique de Montreal in the Department of Computer and Software Engineering. His research interests include design methods for emerging (nano)technologies and embedded systems, including nanophotonic interconnects and reconfigurable architectures. He has authored or co-authored over 70 scientific publications including journal articles, book chapters, patent and conference papers, and held pivotal positions in organizing various international conferences. He is a guest editor for IEEE Transactions on Multi-Scale Computing Systems and general chair of OPTICS workshop.
Professor Subhasish Mitra is Professor of Electrical Engineering and of Computer Science at Stanford University, where he directs the Stanford Robust Systems Group and co-leads the Computation thrust of the Stanford SystemX Alliance. He is also a faculty member of the Stanford Neurosciences Institute. Before joining Stanford, he was a Principal Engineer at Intel Corporation. He received his Ph.D. in Electrical Engineering from Stanford. Prof. Mitra served on the Defense Advanced Research Projects Agency's (DARPA) Information Science and Technology Board as an invited member. He is a Fellow of the ACM and the IEEE.
Barney Maccabe currently serves as the Director for the Computer Science and Mathematics Division at Oak Ridge National Laboratory (ORNL). The division has over 100 technical staff working in a wide range of areas, including computational and applied mathematics; discrete systems; data analysis, visualization, management, and engineering; programming models, and tools; performance modeling, measurement, and analysis; system software; and emerging technologies. Prior to joining ORNL in January of 2009, Dr. Maccabe served on the Computer Science faculty at the University of New Mexico where he also served as director of the UNM Center for High Performance Computing and the CIO for the university. Much of his work has focused on the research related to lightweight approaches in HPC systems. Working in collaboration with staff at Sandia National Laboratories, he was involved in the design and development of a series of lightweight operating systems, starting with SUNMOS (Sandia-UNM OS) for the Intel Paragon back in 1990. This collaboration has grown over the years to include a large collection of collaborators with a current emphasis on lightweight virtualization technologies aimed at supporting application composition in HPC system. Barney earned his B.S. in Mathematics from the University of Arizona in 1977 and his M.S. and Ph.D. in Information and Computer Sciences from the Georgia Institute of Technology in 1980 and 1982, respectively.
Concluding remarks and Adjourn